1. Technical Field
This invention relates to data communications. More specifically, the invention relates to digital scaling to limit clock jitter in video transmission through multiple stages.
2. Description of the Related Art
Some display applications require transmission of video content through multiple stages in a daisy chain, each with a switch allowing that stage's video stream to be selected between the video stream from the preceding stage and the video stream from another source at each stage. As the video stream proceeds from one stage to the next across multiple links, the jitter content in the clocking accumulates. This jitter creates an inherent limitation to the number of links that can be timed without correction. When the jitter exceeds the specification for the link technology, the video data is corrupted.
This process is complicated by the fact that the video stream may be transmitted at any of a variety of frequencies. Although the downstream stages could re-clock the video if it were always sent at the same frequency, it is problematic for these downstream stages to anticipate the changeable video frequency and to create the necessary low-jitter clock in programmable logic.
FIG. 1 shows a conventional method of daisy-chaining digital video signals through multiple stages, each having its own host system. On each host system such as a system 10, a signal containing digital video from the preceding system enters through a receiver chip (‘RX’) 11. The host selects either its own video stream (from the ‘VGA’ chip) 12 or passes through the stream from the preceding stage, using a multiplexer (‘MUX’) 13. The multiplexer switches the data signals, the control signals, and the clock into the transmitter (‘TX’) 14, which outputs through a connection to the next host system of RX 15, VGA 16, MUX 17 and TX 18.
Since jitter accumulates on a clock signal whenever it passes through additional circuitry, the jitter arriving through the ‘RX’ device is aggravated by the multiplexer and transmitter circuitry as it passes to the next host stage.
FIG. 2 shows a conventional method of reducing the jitter accumulation by creating a new clock at each stage of the video switching. In a host system such as a system 20, either the digital video from the preceding host system entering through a receiver chip (‘RX’) 21 or the digital video from own video stream (from the ‘VGA’ chip) 22 is selected using a multiplexer 23. The selected video is gated with a new clock (‘OSC’) 24 before being transmitted using a transmitter (‘TX’) 25, which outputs through a connection to the next host system of RX 26, VGA 27, MUX 28, OSC 29 and TX 30.
If the jitter characteristic of the new clock is better than the received clock, then the accumulation will be slower. If the new clock has extremely small jitter (such as from a crystal source), then the jitter accumulation will be so small as to allow a number of stages to be connected in series.
However, there are still problems in such schemes. The phase of the new clock must be matched to the phase of the data and control signals arriving through the receiver, to guarantee proper setup and hold margins at each transmitter input. Adjusting the phase is difficult for a design handling multiple video frequencies. A system with multiple possible video frequencies will also require a re-programmable clock that always maintains very small jitter. Each stage of the chain must know the required frequency for data received by it from earlier stages. This is a problem for general-purpose systems where multiple video frequencies are used.
Therefore, there is a need for a new scheme to reduce clock jitter during video transmission across multiple stages without the necessity of adding a re-programmable clock source at each stage.